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smb113a/b/smb117/a preliminary information ? summit microelectronics, inc. 2007 757 n. mary avenue ? sunnyvale ca 94085 phone 408 523-1000 ? fax 408 523-1266 http://www.summitmicro.com/ 2111 2.6 9/16/2010 1 introduction figure 1 ? applications schematic featuring the smb113a/b/117 / a programmable dc-dc controllers. note: this is an applications example only. some pins, components and values are not shown. ? digital programming of all major parameters via i 2 c interface and non-volatile memory ? output voltage set point ? input/battery voltage monitoring ? output power-up/down sequencing ? digital soft-start and output slew rate ? dynamic voltage control of all outputs ? uv/ov monitoring of all outputs ? enable/disable outputs independently ? user friendly graphical user interface (gui) ? four synchronous step-down output channels ? integrated reset monitor ? +2.7v to +6.0v input range ? highly accurate output voltage: <1.5% ? factory programmable dead times ? 0% to 100% duty cycle operation ? undervoltage lockout (uvlo) with hysteresis ? 250khz (smb117a), 400khz (smb117), 800khz (smb113a), 1mhz (smb113b) operating frequency ? 96 bytes of user configurable nonvolatile memory applications ? car & marine navigation systems ? set-top boxes ? tvs ? ddr memory ? mobile computing/pdas ? office equipment ? dmb systems the smb113a/b and smb117/a ar e highly integrated and flexible four-channel power managers designed for use in a wide range of applications. t he built-in digital programmability allows system designers to custom tailor the device to suit almost any multi-channel power supply application from digital camcorders to set-top boxes. complete with a user friendly gui, all programmable settings, including output voltages and input/output voltage monitoring, can be customized with ease. the smb113a/b and smb117/a integrate all the essential blocks required to implement a complete four-channel power subsystem consisting of four synchronous step-down ?buck? controllers. additionally sophi sticated power control/monitoring functions required by complex systems are built-in. these include digitally programmable output voltage set point, power- up/down sequencing, enable/disable, dynamic voltage management and uv/ov monitoring on all channels. the integration of features and built-in flexibility of the smb113a/b and smb117/a allows the system designer to create a ?platform solution? that can be easily modified via software without major hardware changes. combined with the re-programmability of the smb113a/b and smb117/a, this facilitates rapid design cycles and proliferation from a base design to future product generations. the smb113a/b and smb117/a are suited to a wide variety of applications with an input range of +2.7v to +6.0v. higher input voltage operation can easily be implemented with a small number of external components. output voltages are extremely accurate (<1.5%). communication is accomplished via the industry standard i 2 c bus. all user-programmed settings are stored in non-volatile eeprom of which 96 bytes may be used as general-purpose memory. the devices are offered in both the commercial and the industrial operating temperature range. the package type is a lead-free, rohs compliant, 5x5 qfn-32. simplified applications drawing features & applications high-power, four-channe l programmable dc-dc sy stem power managers smb113a/b +0.5v to vin (prog.) @ 1.5a/5a +0.5v to vin (prog.) @ 1.5a/5a +2.7v to +6.0v or li-ion cpu core analog/rf i2c/smbus 4 step- down (buck) channels system control and monitoring reset output (power good) enable input +0.5v to vin (prog.) @ 1.5a/5a memory, i/o +0.5v to vin (prog.) @ 1.5a/5a dsp/codec reset monitor reset input smb117/a +0.5v to vin (prog.) @ 5a/10a +0.5v to vin (prog.) @ 5a/10a +2.7v to +6.0v or li-ion cpu core analog/rf i2c/smbus 4 step- down (buck) channels system control and monitoring reset output (power good) enable input +0.5v to vin (prog.) @ 5a/10a memory, i/o +0.5v to vin (prog.) @ 5a/10a dsp/codec reset monitor reset input
smb113a/b/smb117/a preliminary information summit microelectronics, inc. 2111 2.6 9/16/2010 2 the smb113a/b and smb117/a are fully programmable dc-dc controllers that incorporate power delivery and advanced power monitoring and control functionality. the devices integrate four synchronous ?buck? step- down controllers in a space saving package. the smb113a uses a fixed 800khz whereas the smb113b uses a fixed 1mhz, the smb117 a fixed 400khz and the smb117a a fixed 250khz pulse width modulation (pwm) control circuit. a type-three voltage mode compensation network is used offering a cost effective solution without compromising transient response performance. by utilizing external n- and p? type mosfet transistors the efficiency and load current level can be customized to fit a wide array of system requirements. the smb113a/b and smb117/a contain four buck outputs capable of producing an output voltage less than the input voltage. each buck output voltage is set by an internal resistor divider and a programmable voltage reference. the integrated re sistor divider eliminates the cost and space necessary for external components and has several programmable values. through the programmability of the reference and the resistor divider, practically any output voltage smaller than the battery can be produced without the need to change external components. the smb113a/b and smb117/a are capable of power- on/off cascade sequencing where each channel can be assigned one of four unique sequence positions. during sequencing each channel in a given sequencing position is guaranteed to reach its programmed output voltage before the channel(s) occupying the next sequence position initiate their respective soft-start sequence. a unique programmable delay exists between each power on/off sequence position. in addition to power on/off sequencing all supplies can be powered on/off individually through an i 2 c command or by assertion of the enable pin. each output voltage is monitored for under-voltage and over-voltage (uv/ov) conditions, using a comparator- based circuit where the output voltage is compared against an internal programmable reference. an additional feature of the output voltage monitoring is a programmable glitch filter cap able of digitally filtering a transient ov/uv fault condition from a true system error. when a fault is detected for a period in excess of the glitch filter, all supplies may be sequenced down or immediately disabled and an output status pin can be asserted. the current system status is always accessible via internal regist ers containing the status of all four channels. the smb113a/b and smb117/a also possess an under-voltage lockout (uvlo) circuit to ensure the devices will not power up until the input voltage has reached a safe operating voltage. the uvlo function exhibits hysteresis, ensuring that noise or a brown out voltage on the supply rail does not inadvertently lead to a system failure. the smb113a/b and smb117/a provide dynamic voltage management over all of their output voltages. through an i 2 c command, all output voltage levels can be increased or decreased to a pre-programmed level. in addition, each output is sl ew rate limited by soft-start circuitry that is user-programmable and requires no external capacitors. all programmable settings on the smb113a/b and the smb117/a are stored in non-volatile registers and are easily accessed and modified ov er an industry standard i 2 c serial bus. for fastest prototype development times summit offers an evaluation card and a graphical user interface (gui). general description
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 3 typical application figure 2 ? typical application schematic smb113a/b (smb117/a) comp2_ch3 vm_ch3 gnd vbatt sda scl +0.8v to vin @ 5a (10a) vin: +2.7v to +6.0v vddcap hvsup3 pwren lsdrv_ch3 comp1_ch3 hsdrv_ch3 comp2_ch2 vm_ch2 +0.8v to vin @ 5a (10a) hvsup2 lsdrv_ch2 comp1_ch2 hsdrv_ch2 comp2_ch1 vm_ch1 +0.8v to vin @ 5a (10a) hvsup1 lsdrv_ch1 comp1_ch1 hsdrv_ch1 comp2_ch0 vm_ch0 +0.8v to vin @ 5a (10a) hvsup0 lsdrv_ch0 comp1_ch0 hsdrv_ch0 healthy/nreset host_reset
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 4 internal block diagram vddcap deadtime + ? oa level shifter + ? + ? glitch filter glitch filter clamp duty cycle limit over voltage detection 100k digital to analog converter under voltage detection channel 0,1,2,3 synchronous buck pwm converter hsdrv[0,1,2,3] lsdrv[0,1,2,3] comp1_ch[0,1,2,3] comp2_ch[0,1,2,3] vm_ch[0,1,2,3] vref vref osc fixed 250/400/ 800/1000khz max limit low limit z z z z z + ? pwren0 hvsup[0,1,2,3] vref + ? level shifter + ? vbatt zz dq bandgap vref 2.5v regulator vdd_cap gnd uv2 scl sda i 2 c/smbus z uv1 sequencing and monitoring logic enable z z figure 3 ?smb113a/b and smb117/a internal block diagram. programmable functional blocks include: level shifters, digital to analog converter and the vm_ch[0,1,2,3] voltage dividers.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 5 pin description pin number pin type pin name pin description 1 out hsdrv_ch0 the hsdrv_ch0 (channel 0 high-side driver) pin is the upper switching node of the channel 0 synchronous step-down buck controller. attach to the gate of p-channel mosfet. a delay exists between the assertion of hsdrv_ch0 and assertion of lsdrv_ch0 to prevent excessive current flow during switching. 2 out healthy (nreset) the healthy pin is an open drain output. high when all enabled output supplies are within the programmed levels. healthy will ignore any disabled supply. there is a programmable glitch filter on the under-voltage and over-voltage sensors so that short transien ts outside of the limits will be ignored by healthy. this pin can also be programmed to act as a reset output (nreset). in this case, it releases with a programmable delay after all outputs are valid. when used, this pin should be pulled high by an external pull-up resistor. 3 in comp1_ch0 the comp1_ch0 (channel 0 primary compensation) pin is the primary feedback input of t he channel 0 step-down buck controller. the comp1_ch0 pin is internally connected to a programmable resistor divider. 4 in comp2_ch0 the comp2_ch0 (channel 0 secondary compensation) pin is the secondary feedback input of the channel 0 step-down buck controller. 5 in vm_ch0 the vm_ch0 (channel 0 voltage monitor) pin connects the channel 0 step-down controller output. internally the vm_ch0 pin connects to a programmable resistor divider. 6 i/o sda sda (serial data) is an open drain bi-directional pin used as the i 2 c data line. sda must be tied high through a pull-up resistor. 7 in scl scl (serial clock) is an open drain input pin used as the i 2 c clock line. scl must be tied high through a pull-up resistor. 8 out lsdrv_ch1 the lsdrv_ch1 (channel 1 low-side driver) pin is the lower switching node of the channel 1 synchronous step-down buck controller. attach to the gate of n-channel mosfet. 9 pwr hvsup1 channel 1 high voltage supply for channel 1 buck driver. 10 out hsdrv_ch1 the hsdrv_ch1 (channel 1 high-side driver) pin is the upper switching node of the channel 1 synchronous step-down buck controller. attach to the gate of p-channel mosfet. a delay exists between the assertion of hsdrv_ch1 and assertion of lsdrv_ch1 to prevent excessive current flow during switching. 11 in host_reset the host_reset pin is an active high reset input. when this pin is asserted high, the nreset output will immediately go low. when host_reset is brought low, nreset will go high after a programmed reset delay. when pin 2 is used as a healthy output, this pin needs to be attached to gnd or vbatt via a resistor. 12 in comp1_ch1 the comp1_ch1 (channel 1 primary compensation) pin is the primary compensation input of the channel 1 step-down buck controller. the comp1_ch1 pin is internally connected to a programmable resistor divider. 13 in comp2_ch1 the comp2_ch1 (channel 1 secondary compensation) pin is the secondary compensation inpu t of the channel 1 step-down buck controller.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 6 pin description pin number pin type pin name pin description 14 in vm_ch1 the vm_ch1 (channel 1 voltage monitor) pin connects the channel 1 step-down controller output. internally the vm_ch1 pin connects to an internal programmable resistor divider. 15 cap vdd_cap the vdd_cap (vdd capacitor) pin is an external capacitor input used to filter the internal supply. 16 pwr vbatt power supply to part. 17 out lsdrv_ch2 the lsdrv_ch2 (channel 2 low-side driver) pin is the lower switching node of the channel 2 synchronous step-down buck controller. attaches to the gate of n-channel mosfet. 18 pwr hvsup2 channel 2 high voltage supply for channel 2 buck driver. 19 out hsdrv_ch2 the hsdrv_ch2 (channel 2 high- side driver) pin is the upper switching node of the channel 2 synchronous step-down buck controller. attach to the gate of p-channel mosfet. a delay exists between the assertion of hsdrv_ ch2 and assertion of lsdrv_ch2 to prevent excessive current flow during switching. 20 in comp2_ch2 the comp2_ch2 (channel 2 secondary compensation) pin is the secondary compensation input of the channel 2 step-down buck controller. 21 in comp1_ch2 the comp1_ch2 (channel 2 primary compensation) pin is the primary compensation input of the channel 2 step-down buck controller. each pin is internally connected to a programmable resistor divider. 22 in vm_ch2 the vm_ch2 (channel 2 voltage monitor) pin connects the channel 6 step-down controller output. internally the vm_ch2 pin connects to an internal programmable resistor divider. 23 out lsdrv_ch3 the lsdrv_ch3 (channel 3 low-side driver) pin is the lower switching node of the channel 3 synchronous step-down buck controller. attaches to the gate of n-channel mosfet. 24 pwr hvsup3 channel 3 high voltage supply for channel 3 buck driver. 25 out hsdrv_ch3 the hsdrv_ch3 (channel 3 high- side driver) pin is the upper switching node of the channel 3 synchronous step-down buck controller. attach to the gate of p-channel mosfet. a delay exists between the assertion of hsdrv_ ch3 and assertion of lsdrv_ch3 to prevent excessive current flow during switching. 26 in pwren the pwren (power enable) pin is a programmable input used to enable (disable) selected supplies. this pin can also be programmed to latch and act as a debounced, manual push button input. active high when level triggered, active low when used as a push- button input. when unused this pin should be tied to a solid logic level. 27 in comp2_ch3 the comp2_ch3 (channel 3 secondary compensation) pin is the secondary compensation input of the channel 3 step-down buck controller. 28 in comp1_ch3 the comp1_ch3 (channel 3 primary compensation) pin is the primary compensation input of the channel 3 step-down buck controller. each pin is internally connected to a programmable resistor divider.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 7 pin description pin number pin type pin name pin description 29 in vm_ch3 the vm_ch3 (channel 3 voltage monitor) pin connects the channel 3 step-down controller output. internally the vm_ch3 pin connects to an internal programmable resistor divider. 30 pwr gnd ground 31 out lsdrv_ch0 the lsdrv_ch0 (channel 0 low-side driver) pin is the lower switching node of the channel 0 sync hronous step-down buck controller. attach to the gate of n-channel mosfet. 32 pwr hvsup0 channel 0 high voltage supply used to power the channel 0 buck driver. pad pwr gnd exposed metal (thermal) pad on bottom of smb113a/b and smb117/a. the thermal pad of the qfn package must be connected to the pcb gnd.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 8 package and pin description top view gnd smb113a/b/smb117/a 5mm x 5mm qfn-32 1 2 3 13 vm_ch3 4 vm_ch2 10 hsdrv_ch3 12 11 28 27 26 scl comp1_ch3 comp1_ch2 comp2_ch2 5 6 7 8 9 comp2_ch3 24 23 22 25 17 14 16 vdd_cap 15 18 20 21 hvsup2 hsdrv_ch2 lsdrv_ch2 19 gnd sda hvsup3 vbatt 32 31 30 29 pwren lsdrv_ch3 lsdrv_ch0 hvsup0 hsdrv_ch0 comp1_ch0 comp2_ch0 vm_ch0 lsdrv_ch1 hvsup1 hsdrv_ch1 comp1_ch1 comp2_ch1 vm_ch1 host_reset healthy (nreset)
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 9 absolute maximum ratings recommended operating conditions temperature unde r bias .................... -55 c to +125 c storage temper ature .......................... -65 c to +150 c terminal voltage with respect to gnd: vbatt supply voltage ................... -0.3v to +6.5v hvsup supply voltage .................. -0.3v to +6.5v all others ...................................... -0 .3v to vbatt output short circuit current ................. ????100ma reflow solder temper ature (30 secs) ............... +260 c junction temperature ........................................ +150 c esd rating per je dec ..................................... +2000v latch-up testing per jedec ............................. 100ma commercial temperature range ............... 0c to +70c industrial temperature ra nge ................ -40c to +85c vbatt supply voltage ........................... +2.7v to +6.0v hvsup supply voltage ........................... +2.7v to +6.0v all others................................................. gnd to vbatt package thermal resistance ( ja ), 32-lead qfn (thermal pad connected to pcb). ...................... 37.2c/w moisture classification level 3 (msl 3) per j-std-020 reliability characteristics data retentio n ................................................ 100 years endurance ................................................ 100,000 cycle temperature range ................................ -40c to +85c note - the device is not guaranteed to function outside it s operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. exposure to any absolute maximum rating for exte nded periods may affect device performance and reliability. dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit vbatt input supply voltage input supply voltage (operational), note 4 2.7 6.0 v v hvsup buck driver supply voltage gate drive voltage 2.7 6.0 v v uvlo under-voltage lockout vbatt rising 2.2 2.3 v vbatt falling 1.9 2.0 v battsr required input supply voltage slew-rate input supply voltage rising 0.037 v / msec i dd-monitor monitoring current all voltage inputs monitored. no supplies switching, vbatt at 4.2v. 290 400 a i dd-active active current total current all channels enabled. no load. vbatt at 4.2v. note 2. 1.2 2.0 ma vdd_cap internal supply, present on vdd_cap pin no load 2.4 2.5 2.6 v oscillator f osc oscillator frequency smb113b 875 1000 1125 khz smb113a 720 800 880 smb117 360 400 440 smb117a 212 250 288 o pp lt oscillator peak-to-peak 1 v ? f sv frequency stability for voltage 0.1 %/v ? f st frequency stability for temperature +25c to +70c, f osc = 800khz 0.18 khz/ c +25c to +85c, f osc = 800khz 0.22
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 10 dc operating characteristics (continued) ( over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit error amplifier a vol open loop voltage gain at dc 60 db bw frequency bandwidth at a vol = 0 db 30 mhz i source output source current at 0.5v 20 a i sink output sink current at 0.5v 800 a output block v out voltage set point range. 100% maximum duty cycle vbatt= 4.2v, i load =0 v out = v batt x (duty cycle) 0.5 4.2 v vbatt= 6.0v, i load =0 v out = v batt x (duty cycle) 0.5 6.0 ? v out output accuracy, excluding external resistor divider 1 commercial temperature range -1.5 +1.5 % industrial temperature range -2.0 +2.0 r drvh hsdrv on resistance output high 2 ? output low 2 r drvl lsdrv on resistance output high 2 output low 2 v comp1 feedback voltage reference comp1 pin programmable in 4mv steps 1.0 v d.c. 100% max duty cycle high duty cycle 100 % low duty cycle, note 3 35 90% max duty cycle high duty cycle, note 3 70 low duty cycle 0 logic levels v ih input high voltage 0.7 x vdd_cap 6.0 v v il input low 0 0.3 x vdd_cap v v ol open drain outputs i sink = 1ma 0 0.4 v
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 11 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit programmable monitoring thresholds v puv1 programmable uv1 threshold programmable uv1 threshold voltage measured on vbatt pin in 150 mv increments 2.55 3.60 v v puv2 programmable uv2 threshold programmable uv2 threshold voltage measured on vbatt pin in 150 mv increments 2.55 3.60 v ? v puv2 uv2 accuracy 2 % ? v puv1 uv1 accuracy 2 % p uvth programmable under-voltage threshold output voltage relative to nominal operating voltage. note 3. -3 -5 -7 % -8 -10 -12 -12 -15 -18 -16 -20 -24 p ovth programmable over-voltage threshold output voltage relative to nominal operating voltage. note 3. +3 +5 +7 % +8 +10 +12 +12 +15 +18 +16 +20 +24 note 1: voltage accuracies are only guaranteed for factory-progr ammed settings. changing the output voltage from that reflected in the customer specific csir code might result in inaccu racies exceeding those specified above by 1%. note 2: for more accurate active current levels under seve ral load conditions, summit?s proprie tary design software can be used . contact the factory for more information. note 3: guaranteed by design and characterization ? not 100% tested in production. note 4: contact the factory for designs that require an input voltage lower than 4.5v.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 12 ac operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) note 5 symbol description conditions min typ max unit t ppto programmable power-on sequence timeout period. programmable power-on sequence position to sequence position delay. 1.5 ms 12.5 25 50 t dpoff programmable power-off sequence timeout period. programmable power-off sequence position to sequence position delay. 1.5 ms 12.5 25 50 t pst programmable sequence termination period time between active enable in which corresponding outputs must exceed there programmed under voltage threshold. if exceeded, a force shutdown will be initiated. off ms 50 100 200 t pgf programmable glitch filter period for which fault must persist before fault triggered actions are taken. 0 s 8 t reset reset timeout period applicable when healthy pin is used as an nreset output pin. programmable time following assertion of last supply before nreset pin is released high. 25 ms 50 100 200 sr ref programmable slew rate reference adjustable slew rate factor proportional to output slew rate. 400 v/s 200 100 67 50 33 25 20 channels 0 to 3 t rl ls driver output rise time c g =100pf, v batt =4.2v 4.2 ns t fl ls driver output fall time c g =100pf, v batt =4.2v 4.2 ns t rl hs driver output rise time c g =100pf, v batt =4.2v 2.9 ns t fl hs driver output fall time c g =100pf, v batt =4.2v 2.9 ns t dt driver non-overlap delay high to low transition on hsdrv 30 ns low to high transition on buck hsdrv 60 note 5: timing specifications are 20% shorter for the smb113b device and 60% longer for smb117a.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 13 note 6: guaranteed by design. figure 4 ? i 2 c timing diagram i 2 c-2 wire serial interface ac ope rating characteristics ? 100 khz (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol description conditions 100khz min typ max units f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4.0 s t buf bus free time before new transmission ? note 6 4.7 s t su:sta start condition setup time 4.7 s t hd:sta start condition hold time 4.0 s t su:sto stop condition setup time 4.7 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 s t r scl and sda rise time note 6 1000 ns t f scl and sda fall time note 6 300 ns t su:dat data in setup time 250 ns t hd:dat data in hold time 0 ns ti noise filter scl and sda noise suppression 136 ns t wr_config write cycle time config configuration registers 10 ms t wr_ee write cycle time ee memory array 5 ms t r t f t high t low t su:sta t hd:sta t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t wr (for write operation only) timing diagrams
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 14 smb113a efficiency graphs efficienc y at 3.3v 60 65 70 75 80 85 90 95 100 00.511.52 current (amps) efficienc y ( % ) 5.0v 3.8v 4.2v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 00.511.52 cur r ent ( am ps) efficienc y (%) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 current (am ps) efficienc y (%) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 00.511.52 current (am ps) efficienc y ( % ) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 00.511.52 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 3.4v efficienc y at 2.5v efficienc y at 1.8v efficienc y at 1.2v efficienc y at 1.5v
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 15 0 10 20 30 40 50 60 70 80 90 100 024681012 current (amps) efficiency (%) 1.2v 1.8v 2.5v 3.3v v in = 5.0 volts 2.5 volts buck 2.5v smb117 efficiency graphs efficienc y at 1.2v , 1.8v , 2.5v , 3.3 v
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 16 applications information device operation power supply there are five supply input pins on the smb113a/b and smb117/a: four hvsup pins and the vbatt pin. each supply must be powered from an input voltage between 2.7-6.0 volts. the hvsup1 though hvsup4 are used to power the hsdrv (pmos driver) and lsdrv (nmos driver) outputs. the rail-to-rail swing on the hsdrv and lsdrv pins is equal to the associated hvsup supply voltage. the vbatt pin is internally regulated to 2.5v. this 2.5v supply is then filtered on the vdd_cap pin and used to power all internal circuitry. the vbatt pin is monitored by an under-voltage lockout (uvlo) circuit, which prevents the device from turning on when the voltage at this node is less than the uvlo threshold. output voltage all output voltages on the smb113a/b and smb117/a can be set via the non-volatile configuration registers. each of the four step-down output voltages on the smb113a/b and smb117/a can be adjusted for 100% duty cycle or 0% duty cycle operation. when 100% duty cycle mode is selected, the output voltage can be set up to the input voltage on the device, while the minimum output voltage is limited to the min duty cycle specification in the dc operating characteristics section. when the 0% duty cycle mode is selected, the maximum duty cycle is limited to the max duty cycle specification in the dc operating characteristics section. power-on/off control sequencing can be initiated: automatically, by a volatile i 2 c power on command, or by asserting the pwren pin. when the pwren pin is programmed to initiate sequencing, it can be level or edge triggered. the pwren input has a programmable de-bounce time of 100, 50, or 25ms. the de-bounce time can also be disabled. when configured as a push-button enable, pwren must be asserted longer than the de-bounce time before sequencing can commence, and pulled low for the same period to disable the channels. enable each output can be enabled and disable by an enable signal. the enable signal is can be provided from either the pwren pin or by the contents of the enable register. when enabling a channel from the enable register, the register contents default stat e must be set so that the output will be enabled or disabled following a por (power on reset). the default state is programmable. cascade sequencing each channel on the smb113a/b and smb117/a may be placed in any one of 4 unique sequence positions, as assigned by the config urable non-volatile register contents. the smb113a/b and smb117/a navigate between each sequence position using a feedback- based cascade-sequencing circuit. cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. in the event that a channels enable input is not asserted when the channel is to be sequenced on, that sequence position will be skipped and the channel in the next sequence posi tion will be enabled. figure 5 ? power on sequencing waveforms. time = 4ms/devision, scale = 1v/devision ch 1 = 3.3v output (yellow trace) ch 2 = 2.5v output (blue trace) ch 3 = 1.8v output (purple trace) ch 4 = 1.2v output (green trace) power on/off delay there is a programmable delay between when channels in subsequent sequence positions are enabled. the delay is programmable at 50, 25, 12.5 and 1.5ms intervals. this delay is programmable for each of the four sequence positions.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 17 applications information (continued) manual mode the smb113a/b and smb117/a provide a manual power-on mode in which each channel may be enabled individually irrespective of the state of other channels. in this mode, the enable signal has complete control over the channel, and all sequencing is ignored. in manual mode, channels will not be disabled in the event of a uv/ov fault on any output or the vbatt pin. force-shutdown when a battery fault occurs, a uv/ov is detected on any output, or an i 2 c force-shutdown command is issued, all channels will be immediately disabled, ignoring sequence positions or power off delay times. sequence termination timer at the beginning of each sequence position, an internal programmable timer will begin to time out. when this timer has expired, the smb113a/b and smb117/a will automatically perform a force-shutdown operation. this timer is user programmable with a programmable sequence termination period (t pst ) of 50, 100, 200 ms; this function can also be disabled. power off sequencing the smb113a/b and smb117/a have a power-off sequencing operation. during a power off operation, the supplies will be powered off in the reverse order they where powered on in. during the power off sequencing, all enables are ignored. when a power-off command is issued the smb113a/b and smb117/a will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequence position will begin to timeout, after which that channel(s) will be disabled. this process will continue until all channels have been disabled and are off. the programmable if a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. input and output monitoring both products monitor all outputs for under-voltage (uv) and over-voltage (ov) faults. the monitored levels are user programmable, and may be set at 5, 10, 15, and 20 percent of the nominal output voltage. the vbatt pin is monitored for two user programmable uv se ttings. the vbatt uv settings are programmable from 2.55v to 3.45v in 150mv increments. once the uv/ov voltage set points have been violated, the smb113a/b and smb117/a can be programmed to respond in one of three ways, perform: a power-off operation, a fo rce-shutdown operation and-or it can trigger the nreset/healthy pin. soft start the smb113a/b and smb117/a provide a programmable soft-start function for all pwm outputs. the soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. the soft start slew rate is proportional to the product of the output voltage and a slew rate reference. this global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 volts per second. the slew rate control can also be disabled on any channel not requiring the feature. dynamic voltage management the smb113a/b/117/a have two additional voltage settings, dynamic voltage control high and low settings. together with the nominal voltage setting, three pre-determined voltage levels can be used. the three voltage levels are ideal for situations where a core voltage needs to be reduced for power conservation. the dynamic voltage control high and low settings have the same voltage range as the controllers? nominal output voltage. these settings are stored in the non-volatile configurat ion registers and can be set by a write to volatile conf iguration registers. the dynamic voltage control command registers contain two bits for each channel that adjust the output voltages to the high, low or nominal set point after a volatile i2c write command. a seven level dynamic voltage control option is available for channel 3. when enabled, seven level dynamic voltage control allows channel 3 to be dynamically modified to one of seven pre-determined voltage levels. this transition is made by means of a volatile i 2 c write command. when all channels are at their voltage setting, a bit is set in the dynamic voltage control status registers. + ? vref r1 r2 comp1 vout vout= vref* (1 + r2/r1) soft-start slew rate=srref* (1 + r2/r1) figure 6 ? the output voltage is set by the voltage divider . the vref voltage is programmable from 0 to 1.0 volt in 4mv increments via the i 2 c interface
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 18 applications information high voltage operation: while the smb113a has a max input voltage of 6.0v the controller can operate to0 much higher voltages by using the circuit depicted below. by inserting a capacitor, c1, in series with the hsdrv gate signal the hsdrv pin is isolated from the 12v supply, and the ac coupling capacitor acts as a level translator transferring the 0-5v signal from the hsdrv pin to a 12v to 7v (12v-5v = 7v) si gnal at the gate of the pfet. when the gate stops switching the capacitor becomes an open circuit and the gate will be pulled high by r1 turning off the output. the schottky diode and the pull-up resistor are used for dc restoration and as a pull-up respectively. since the converter runs dire ctly from the input supply (12v in this instance) the efficiency is consistent with that of a synchronous conv erter. typical efficiency curves are shown below. 7v lsdrv hsdrv ac coupling capacitor all power comes directly from 12v supply dc restoration c45 22uf c51 0.1uf c1 0.1uf r1 1k schottky c28 22uf c33 0.1uf l1 3.3uh q2(p) q1(n) q6 fdc6420c vout 1 np +12v time 5v time 12v figure 7 ? high-voltage operation
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 19 applications information (continued) figure 8 ? smb113a applications schematic.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 20 applications information (continued) item description vendor / part number qty ref. des. resistors 1 300 , 1/16w, 1%, 0603, smd vishay crcw06033000f 4 r1, r4, r6, r8 2 6.04k , 1/16w, 1%, 0603, smd vishay crcw06036041f 1 r2 3 4.99k , 1/16w, 1%, 0603, smd vishay crcw06034991f 2 r3, r5 4 6.98k , 1/16w, 1%, 0603, smd vishay crcw06036981f 1 r7 5 47 , 1/16w, 1%, 0603, smd vishay crcw06034702f 5 r9, r18, r19, r20, r21 6 3 , 1/16w, 1%, 0603, smd vishay crcw06033r01f 8 r10, r11, r12, r13, r14, r15, r16, r17 7 10k , 1/16w, 1%, 0603, smd vishay crcw06031002f 1 r20 8 300 , 1/16w, 1%, 0603, smd vishay crcw06031000f 4 r22, r23, r24, r27 capacitors 9 0.1uf, 16v, ceramic, x7r, 0603, smd kemet c0603c104k4ractu 15 c1, c3, c6, c8, c16, c21, c26, c28, c31, c33, c34, c36, c38, c40, c42 10 1uf, 10v, ceramic, y5v, 0603, smd panasonic ecj-1vf1a105z 2 c2, c35 11 10uf, 6.3v, ceramic, x5r, 0805, smd kemet c0 805c106k9pactu 9 c4, c25, c27, c29, c37 12 10uf, 25v, ceramic, x7r, 1210, smd tdk c3225x7r1e106m 4 c5, c7, c15, c20, 13 330pf, 50v, ceramic, c0g, 0603, smd murata grm1885c2a331ja01d 1 c9 14 120pf, 50v, ceramic, c0g, 0603, sm d vishay vj0603a 121kxaa 2 c10, c18 680pf, 100v, ceramic, x7r, 0603, smd murata grm188r72a681ka01d 2 c11, c22 15 47pf, 50v, ceramic, np0, 0603, smd panasonic ecj-1vc1h470j 1 c13 16 470pf, 50v, ceramic, x7r, 0603, smd kemet c0603c471k5ractu 2 c17, c12 17 820pf, 50v, ceramic, c0g, 0603, smd murata grm1885c2a331ja01d 2 c14, c19 18 220pf, 50v, ceramic, c0g, 0603, smd murata grm188r72a221ka01d 1 c23 19 1000pf, 50v, ceramic, c0g, 0603, smd vishay vj0603a102kxaa 1 c24 semiconductors 20 mosfet, complementary fair child, fdc6420c 4 q1-q4 21 smb113anc summit microelectronics 1 u1 magnetics 22 inductor, 6.8uh, 2.75a, smd, shielded sumida cdr7d28mnnp- 6r8nc 4 l1-4
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 21 applications information (continued) figure 9 ? applications schematic showing smb113a operation from a +12v input supply . r30 47k d8 q1 npn c18 0.1uf d9 r12 1k r39 100 d3 schottky c20 22uf c22 0.1uf r28 4.99k r13 0 optional push-button enable c46 22uf c47 0.1uf r29 499 c48 330pf c49 22pf c50 3300pf ch3 1 r10 1k d10 c11 0.1uf host_reset 1 vbatt 1 r37 100 c13 0.1uf c25 0.1uf r24 4.99k c40 22uf l2 3.3uh q2(p) q1(n) q4 fdc6420c c41 0.1uf r25 499 c42 330pf c43 22pf c44 3300pf d11 ch1 1 c24 0.1uf pwren0 1 r16 1k d5 schottky c27 22uf c29 0.1uf u1 smb113a hsdrv_ch0 1 healthy 2 comp1_ch0 3 comp2_ch0 4 vm_ch0 5 sda 6 scl 7 lsdrv_ch1 8 hvsup1 9 hsdrv_ch1 10 host_reset 11 comp1_ch1 12 comp2_ch1 13 vm_ch1 14 vddcap 15 vbatt 16 lsdrv_ch2 17 hvsup2 18 hsdrv_ch2 19 comp2_ch2 20 comp1_ch2 21 vm_ch2 22 lsdrv_ch3 23 hvsup3 24 hsdrv_ch3 25 pwren0 26 comp2_ch3 27 comp1_ch3 28 vm_ch3 29 gnd 30 lsdrv_ch0 31 hvsup0 32 r17 0 +12v 1 c19 0.1uf r14 100 l3 3.3uh q2(p) q1(n) q3 fdc6420c c21 0.1uf c30 0.1uf r19 1k d6 schottky c31 22uf c32 0.1uf r20 0 l1 3.3uh ch2 1 q2(p) q1(n) q5 fdc6420c vbatt scl sda vbatt l4 3.3uh q2(p) q1(n) q2 fdc6420c r1 4.99k c5 22uf c7 0.1uf r2 499 c8 330pf c9 22pf c10 3300pf r3 100 vin ch0 1 vin r9 49.9k healthy/nreset 1 np vbatt vin vbatt donglevcc j1 i2c gnd 1 scl 2 gnd3 3 sda 4 rsrv5 5 mr 6 +10v 7 rsrv8 8 +5v 9 rsrv10 10 sda scl donglevcc r7 47k d2 vin sw1 optional for programming smb113a vin c14 0.1uf c15 1uf c1 0.1uf c2 1uf c12 0.1uf r4 1k d1 schottky c16 22uf c17 0.1uf r5 0 d7 5.6v r22 4.99k c34 22uf c35 0.1uf r23 499 c36 330pf c37 22pf c38 3300pf
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 22 applications information (continued) item description- vendor / part number qty ref. des. capacitors 1 0.1uf, 50v, ceramic, x7r, 0603, smd murata grm188r71h104ka93d 19 c1, c3, c7, c11, c13, c12, c14, c17, c18, c19, c21, c22, c24, c25, c29, c30, c32, c35, c41, c47 2 1uf, 25v, ceramic, x5r, 0805, smd murata grm216r61e105ka12 2 c2, c15 3 22uf, 16v, ceramic, x5r, 1210, smd murata grm32er61c226me20l 9 c5, c16, c20, c27, c31, c34, c40, c46 4 330pf, 50v, ceramic, np0, 0603, smd panasonic ecj-1vc1h331j 4 c8, c36, c42, c48 5 22pf, 50v, ceramic, np0, 0603, smd murata grm1885c1h470ja01d 4 c9, c37, c43, c49 6 3300pf, 100v, ceramic, x7r, 0603, smd murata grm188r71h332ka01d 4 c10, c38, c44, c50 resistors 7 499 , 1/10w, 1%, 0603, smd vishay crcw06034990f 4 r2, r23, r25, r29 8 100 , 1/10w, 1%, 0603, smd vishay crcw06031000f 4 r3, r14, r37, r39 9 1k , 1/10w, 1%, 0603, smd vishay crcw06031001f 5 r4, r10, r12, r16, r19 10 0 , 1/10w, 1%, 0603, smd vishay crcw06030r00f 4 r5, r13, r17, r20 11 49.9k , 1/10w, 1%, 0603, smd vishay crcw06034992f 4 r6, r7, r8, r30 12 2k , 1/10w, 1%, 0603, smd vishay crcw06032001f 1 r9 13 4.99k , 1/10w, 1%, 0603, smd vishay crcw06034991f 4 r1, r22, r24, r28 semiconductors 14 diode schottky, 20v, 200ma, ss-mini panasonic ma2sd2400l 4 d1, d3, d5, d6 15 diode, schottky, 40v, 500ma sod-123 diodes inc. b0540w-7 5 d2, d8, d9, d10, d11 16 led, red, 0805, smd lumex sml-lxt0805srw- tr 2 d4 17 zener diode, 5.6v, 500mw, sod-123 on semi mmsz5v6t1g 1 d7 18 npn, 40v, 1a, sot-89 zetex fcx491a 1 q1 19 mosfet, complementary, 20v, ssot-6 analog power am3520c 4 q2, q3, q4, q5 20 smb113a summit microelectronics 1 u1 magnetics 21 inductor 3.3uh tdk hcp0703-3r3-r 4 l1, l2, l3, l4
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 23 applications information (continued) figure 10 ? applications schematic showing smb117 operation from a +5v input supply with 10a output current capability . r30 47k r11 0 r39 100 c20 22uf r28 10k c22 0.1uf r13 0 c46 22uf c47 0.1uf r29 499 c48 330pf c49 22pf c50 3300pf ch3 1 c11 0.1uf host_reset 1 tp15 vbatt 1 r37 100 c13 0.1uf r24 10k q6 fds6675bz 1 2 3 4 5 6 7 8 l2 2.0uh c40 22uf c41 0.1uf q7 fds6680as 1 2 3 4 5 6 7 8 r25 499 c42 330pf d10 c43 22pf c44 3300pf ch1 1 pwren0 1 c27 22uf c29 0.1uf r17 0 u1 smb117 hsdrv_ch0 1 healthy 2 comp1_ch0 3 comp2_ch0 4 vm_ch0 5 sda 6 scl 7 lsdrv_ch1 8 hvsup1 9 hsdrv_ch1 10 host_reset 11 comp1_ch1 12 comp2_ch1 13 vm_ch1 14 vddcap 15 vbatt 16 lsdrv_ch2 17 hvsup2 18 hsdrv_ch2 19 comp2_ch2 20 comp1_ch2 21 vm_ch2 22 lsdrv_ch3 23 hvsup3 24 hsdrv_ch3 25 pwren0 26 comp2_ch3 27 comp1_ch3 28 vm_ch3 29 gnd 30 lsdrv_ch0 31 hvsup0 32 c19 0.1uf r14 100 l3 2.0uh c21 0.1uf c31 22uf c32 0.1uf r20 0 l1 2.0uh ch2 1 vbatt optional for programming smb113a optional push-button enable scl sda vbatt l4 2.0uh r1 10k c5 22uf c7 0.1uf r2 499 c8 330pf c9 22pf c10 3300pf r3 100 vbatt ch0 1 r9 2k healthy/nreset 1 r18 0 q10 fds6675bz 1 2 3 4 5 6 7 8 q11 fds6680as 1 2 3 4 5 6 7 8 d9 vbatt vbatt donglevcc j1 i2c gnd 1 scl 2 gnd3 3 sda 4 rsrv5 5 mr 6 +10v 7 rsrv8 8 +5v 9 rsrv10 10 sda scl donglevcc r7 47k d2 vbatt q12 fds6675bz 1 2 3 4 5 6 7 8 q13 fds6680as 1 2 3 4 5 6 7 8 sw1 vbatt q8 fds6675bz 1 2 3 4 5 6 7 8 q9 fds6680as 1 2 3 4 5 6 7 8 d11 d8 vbatt r15 0 r21 0 c14 0.1uf c15 1uf c1 0.1uf c2 1uf c16 22uf c17 0.1uf r5 0 r22 10k c34 22uf c35 0.1uf r23 499 c36 330pf c37 22pf c38 3300pf
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 24 applications information (continued) item description- vendor / part number qty ref. des. capacitors 1 0.1uf, 50v, ceramic, x7r, 0603, smd murata grm188r71h104ka93d 19 c1, c3, c7, c11, c13, c12, c14, c17, c18, c19, c21, c22, c24, c25, c29, c30, c32, c35, c41, c47 2 1uf, 25v, ceramic, x5r, 0805, smd murata grm216r61e105ka12 2 c2, c15 3 22uf, 16v, ceramic, x5r, 1210, smd murata grm32er61c226me20l 9 c5, c16, c20, c27, c31, c34, c40, c46 4 330pf, 50v, ceramic, np0, 0603, smd panasonic ecj-1vc1h331j 4 c8, c36, c42, c48 5 22pf, 50v, ceramic, np0, 0603, smd murata grm1885c1h470ja01d 4 c9, c37, c43, c49 6 3300pf, 100v, ceramic, x7r, 0603, smd murata grm188r71h332ka01d 2 c10, c38, c44, c50 resistors 7 499 , 1/10w, 1%, 0603, smd vishay crcw06034990f 4 r2, r23, r25, r29 8 100 , 1/10w, 1%, 0603, smd vishay crcw06031000f 4 r3, r14, r37, r39 9 1k , 1/10w, 1%, 0603, smd vishay crcw06031001f 5 r4, r10, r12, r16, r19 10 0 , 1/10w, 1%, 0603, smd vishay crcw06030r00f 4 r5, r13, r17, r20 11 49.9k , 1/10w, 1%, 0603, smd vishay crcw06034992f 4 r6, r7, r8, r30 12 2k , 1/10w, 1%, 0603, smd vishay crcw06032001f 1 r9 13 10k , 1/10w, 1%, 0603, smd vishay crcw06031002f 4 r1, r22, r24, r28 semiconductors 14 diode, schottky, 40v, 500ma sod-123 diodes inc. b0540w-7 5 d2, d12, d13, d14, d15 15 led, red, 0805, smd lumex sml-lxt0805srw- tr 2 d4 16 mosfet, nfet, 20v, sot-8 fairchild fds6680as q7, q9, q11, q13 17 mosfet, pfet, 20v, sot-8 fairchild fds6675bz 4 q6, q8, q10, q12 18 smb117 summit microelectronics 1 u1 magnetics 19 inductor 2.0uh wurth 744314200 4 l1, l2, l3, l4
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 25 applications information (continued) component selection buck outputs: inductor: the starting point design of any and dc/dc converter is the selection of the appropriate inductor for the application. the optimal inductor value will set the inductor current at 30% of the maximum expected load current. the inductors current for a buck converter is as follows: buck: equation 1: f i vin vo v vo l max in * * 3 . 0 * ) ( ? = where vo is the output voltage, vin is the input voltage, f is the frequency, and i max is the max load current. for example: for a 1.2v out put and a 3.6v input with a 500ma max load, and a 1mhz switching frequency the optimal inductor value is: uh e l 3 . 5 6 1 * 5 . 0 * 3 . 0 * 6 . 3 ) 2 . 1 6 . 3 ( 2 . 1 = ? = choosing the nearest standard inductor value we select a 5.6uh inductor. it is important that the inductor has a saturation current level greater than 1.2 times the max load current. other parameters of inte rest when selecting an inductor are the dcr (dc winding resistance). this has a direct impact on the efficiency of the converter. in general, the smaller the size of the inductor is the larger the resistance. as the dcr goes up the power loss increases according to the i 2 r relation. as a result choosing a correct inductor is often a trade off between size and efficiency. input capacitor each converter should have a high value low impedance input (or bulk) capacitor to act as a current reservoir for the converter st age. this capacitor should be either a x5r or x7r mlcc (multi-layer-ceramic capacitor). the value of this capacitor is normally chosen to reflect the ratio of the input and output voltage with respect to the output capacitor. typical values range from 2.2uf to 10uf. for buck converters, the input capacitor supplies square wave current to the inductor and thus it is critical to place this capacitor as close to the pfet as possible in order to minimize trace inductance that would otherwise limit the rate of change of the current. output capacitor each converter should have a high value low impedance output capacitor to act as a current reservoir for current transi ents and to. this capacitor should be either a x5r or x7r mlcc. for a buck converter, the val ue of this capacitance is determined by the maximum expected transient current. since the converter has a finite response time, during a load transient the current is provided by the output capacitor. sinc e the voltage across the capacitor drops proportionally to the capacitance, a higher output capacitor reduces the voltage drop until the feedback loop can react to increase the voltage to equilibrium. the voltage drop can be calculated according to: equation 2 : where i is the load or transient current, t is the time the output capacitor is sup porting the output and c is the output capacitance. typical values range from 10uf to 44uf. other important capacitor parameters include the equivalent series resistance (e.s.r) of the capacitor. the esr in conjunction with the ripple current determines the ripple voltage on the output, for typical values of mlcc the esr ranges from 2-10m . in addition, carful attention must be paid to the voltage rating of the capacitor the voltage rating of a capacitor must never be exceeded. in addition, the dc bias voltage rating can reduce the measured capacitance by as much as 50% when the voltage is at half of the max rating, make sure to look at the dc bias de-rating curves when selecting a capacitor. mosfets when selecting the appropriate fet to use attention must be paid to the gate to source rating, input capacitance, and maximum power dissipation. most fets are specified by an on resistance (rds on ) for a given gate to source voltage (v gs ). it is essential to ensure that the fets used will always have a v gs voltage grater then the minimum value shown on the datasheet. it is worth noting that the specified v gs voltage must not be confused with the threshold voltage of the fet. c t i v * =
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 26 applications information (continued) the input capacitance must be chosen such that the rise and fall times specified in the datasheet do not exceed ~5% of the switching period. to ensure the maximum load current will not exceed the power rating of the fet, the power dissipation of each fet must be determined. it is important to look at each fet individually and then add the power dissipation of complementary fets after the power dissipation over one cycle has been determined. the power dissipation can be approximated as follows: equation 3: on l dson t i r p * * ~ 2 where t on is the on time of the primary switch. t on can be calculated as follows: equations 4, 5: t v v pfet buck t v v nfet buck in o in o * : * ) 1 ( : ? ? ? compensation: summit provides a design tool to called summit power designer? that will automatically calculate the compensation values for a design or allow the system to be customized for a particular application. the power designer software can be found at http://www.summitmicro.com/prod_select/xls/summitp owerdesigner_install.zip .
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 27 development hardware & software the end user can obtain the summit smx3200 parallel port programming system or the i 2 c2usb (smx3201) usb programming system for device prototype development. the smx3200(1) system consist of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the latest revisions of all software and an application brief describing the smx3200 and smx3201 are available from the website ( http://www.summitmicro.com ). the smx3200 programming dongle/cable interfaces directly between a pc?s par allel port and the target application; while the smx3201 interfaces directly to the pc?s usb port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software w ill generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smb113a/b or smb117/a via the programming dongle and cable. an example of the connection interface is shown in figure 11. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this w ill ensure proper device operation in the end application. pin 9, 5.0v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200/smx3201 interface cable connector. 9 7 5 3 1 10 8 6 4 2 smb113a/b smb117/a sda scl gnd 0.1 f vbatt figure 11 ? smx3200/smx3201 programmer i 2 c serial bus connections to program the smb113a/b or smb117/a.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 28 i 2 c programming information serial interface access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers, sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating star t and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 7-bit device type identifier (slave address). the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the smb113a/b. the device type identifier for the memory array, the configuration registers an d the command and status registers are accessible with the same slave address. the slave address can be can be programmed to any seven bit number 0000000 bin through 1111111 bin . write writing to the memory or a configuration register is illustrated in figures 12and 13 a start condition followed by the slave address byte is provided by the host; the smb113a/b and smb117/a respond with an acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the smb113a/b and smb117/a respond with an acknowledge; the host then clocks in one byte of data. for memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the smb113a/b or the smb117/a. this is accomplished by issuing a dummy write command, which is a write command that is not followed by a stop condition. a dummy write command sets the address from which data is read. after the dummy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of cons ecutive addresses with the host providing an acknowledge after each byte. after the data is read from the de sired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figure 14for an illustration of the read sequence. configuration registers the configuration registers are grouped with the general-purpose memory. general-purpose memory the 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. the first 48-byte memory block begins at register address pointer a0 hex and the second memory block begins at the r egister address pointer c0 hex ; see table 1. each memory block can be locked individually by writing to a dedicated register in the configuration memory space.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 29 i 2 c programming information (continued) graphical user interface (gui) device configuration ut ilizing the windows based smb113a/b/117/a graphical us er interface (gui) is highly recommended. the software is available from the summit website ( http://www.summitmicro.com ). using the gui in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the smb113a/b and smb117/a. the dongle connects directly to the parallel port of a pc and programs the device through a cable using the i 2 c bus protocol. see figure 11 and the smx3200 data sheet. slave address register type 0000000 bin to 1111111 bin configuration registers are located in 00 hex thru 9f hex general-purpose memory block 0 is located in a0 hex thru bf hex general-purpose memory block 1 is located in c0 hex thru ff hex table 1 ? possible address bytes used by the smb113a/b and the smb117/a.
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 30 s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 12 ? register byte write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 13 ? register page write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k bus address a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 14 ? register read i 2 c programming information (continued)
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 31 package
smb113a/b/smb117/a preliminary information summit microelectronics, inc 2111 2.6 9/16/2010 32 ordering information 113 xxxxxx pin 1 nnnn summit part number manufacturing code part number suffix (contains customer specific ordering requirements) drawing not to scale 113 xxxxxx pin 1 nnnn manufacturing code part number suffix (contains customer specific ordering requirements) drawing not to scale or summit part number the default device ordering number is smb113anc-650l. it is tested over the commercial temperature range. the ordering number i s derived from the customer supplied hex file. new device suffix numbers are assigned to non-default requirements. notice note ? this is a preliminary data sheet that describes a summit that is in pre-production with limited characterization. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect repres entative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc . shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affe ct their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receive s written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 2.6 this document supersedes all previous versions. please check the summit microelectronics inc. web site at http://www.summitmicro.com for data sheet updates. ? copyright 2007 summit microelectronics, inc. programmable power for a green planet? adoc tm is a registered trademark of summit microelectronics inc., i 2 c is a trademark of philips corporation. part marking smb113a n package n = 32-pad qfn summit part number specific requirements are contained in the suffix nnn part number suffix l c c = commercial temperature range blank = industrial l = 100% sn, rohs compliant environmental attribute smb113a, smb113b, smb117 or smb117a t tape & reel subject to change

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